Analog Memory Circuit Parameters Calculation in the Signal Hold Mode
The generalized models of sample and hold circuit in the signal hold mode were proposed and created. Analytical equations for sample and hold circuit parameters calculation and dynamic errors estimation were derived. The sample and hold circuit with diode bridge key simulation results were presented. It was assumed, that signal is serrated, the clock frequency is 250 MHz, and the quantity of binary segments b = 8. The 0,5 μm bipolar integrated technology SPICE models were used for simulation. It was found, that output signal defflection not exceeds one least significant bit value, when hold capacity is 10 pF. It was demonstrated, when circuit model parameters are fixed, the velocity of sample and hold circuit can be increased by decreasing quantity of segments, or precision. Ill. 5, bibl. 7 (in Lithuanian; summaries in English, Russian, and Lithuanian).
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