Simulation of the Integrated Signal Folding Circuit with P–Spice

Abstract

The dynamical characteristics simulation results of the analog signal folding circuit for comparator ADCs were presented. The transient processes at differential folding and comparator stages switching points were simulated using improved models of real transistors and software P – Spice, when folding factor M = 4, 6, 8, 10, 12 and more, and when clock signal’s frequencies are from 6,25 GHz to 4,1 GHz. It has been determined that the optimal folding coefficient is 4–8. When M is larger, the requirements for the comparator sensitivity become more rigid and the signal processing speed becomes lower. E.g., when M = 8, the signal variation speed v = 250 mV / ns, and the comparator sensitivity Δu = 175 mV. When M = 12, v = 125 mV / ns, Δu ≤ 31,5 mV. By simulating the circuit when M > 12, it has been determined that codes were missed. It is related to the nonlinearity of transistor volt–ampere characteristics on the edges of these characteristics. With the aim to increase M > 12, it is necessary to improve sensitivity of comparator, to optimize the input signal dynamic range and to expand the linear part of folding amplifiers transistors volt–ampere characteristics. Ill. 8, bibl. 6 (in English; summaries in English, Russian and Lithuanian).