Signal Simulation in Folding and Interpolating Integrated ADC
The structure of the folding and interpolating analog-to-digital converter, which includes the signal sample and hold, folding and interpolating circuits, the electric circuits of which are formed on the basis of silicon bipolar transistors of the 0.5 μm technology, is presented. The methodology of simulation of dynamic characteristics of the created 8-binary bit converter and calculation of the digital output signal form was developed. The results of simulation of dynamic characteristics of the converter with signal transformation circuits and investigation of frequency parameters are presented. It has been determined that the maximum number of samples per second of such a converter reaches 4·109, and the number of effective bits with the analog signal maximum frequency of 10 MHz is 8. It has been shown that by increasing the analog signal frequency the number of effective bits of the converter decreases and at the 50 MHz frequency it is equal to 6. The investigations have shown that the analog signal maximum frequency of the folding-interpolating ADC can be increased by reducing the folding and interpolation coefficients. When the interpolation coefficient is K = 4 and the folding coefficient is M = 3, the analog signal fmax for the 8-bit converter could be about 1 GHz. Ill. 6, bibl. 7. (in English; summaries in English, Russian and Lithuanian).
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