Calculation of Interpolation Parameters in the Comparator Analog Information Converters

Abstract

The theoretical analysis of interpolation parameters evaluating the influence of folding circuits on the ADC speed and accuracy is made in the paper. The analytical equations are derived and dependences of interpolation parameters on the number of converter bits, the analog signal frequency band width, and the folding coefficient are considered. Equations of for the interpolation error evaluation, depending on the nonlinearity of transfer characteristics of differential amplifiers, folding and interpolation level, were derived. It has been determined that the speed of the interpolating ADC with folding amplifiers strongly depends on the inertness of the interpolating resistor divider circuit and the number of the converter bits. In order to increase the number of the converter bits with the same interpolation coefficient, the circuit inertness must be reduced. A higher interpolation level can be achieved by reducing the speed of the converter. The interpolation error depends on the folding and interpolation coefficients. The lowest interpolation error (0.2 – 0.5 LSB ) can be achieved by selecting a certain linear part length of transfer characteristic of folding differential amplifiers. Ill. 3, bibl. 5 (in English; summaries in English, Russian and Lithuanian).