Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults

Authors

  • R. Beniseviciute
  • L. Butkus
  • R. Seinauskas

Abstract

CMOS integrated circuits layout and transistors faults and coverage by logic gate stuck-at faults checking tests to transistor circuit in this paper are analyzed. The comparable analysis of physical and logical faults by means of complete test sequence is fulfilled. PSPICE and CADENCE modelling systems were applied for faults simulation.

Published

1998-10-29

How to Cite

Beniseviciute, R., Butkus, L., & Seinauskas, R. (1998). Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults. Elektronika Ir Elektrotechnika, 18(5). Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/16035

Issue

Vol. 18 No. 5 (1998)

Section

Articles

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