Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults

R. Beniseviciute; L. Butkus; R. Seinauskas

Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults

Authors

R. Beniseviciute
L. Butkus
R. Seinauskas

Abstract

CMOS integrated circuits layout and transistors faults and coverage by logic gate stuck-at faults checking tests to transistor circuit in this paper are analyzed. The comparable analysis of physical and logical faults by means of complete test sequence is fulfilled. PSPICE and CADENCE modelling systems were applied for faults simulation.

Published

1998-10-29

Issue

Vol. 18 No. 5 (1998)

Section

Articles

License

The copyright for the paper in this journal is retained by the author(s) with the first publication right granted to the journal. The authors agree to the Creative Commons Attribution 4.0 (CC BY 4.0) agreement under which the paper in the Journal is licensed.

By virtue of their appearance in this open access journal, papers are free to use with proper attribution in educational and other non-commercial settings with an acknowledgement of the initial publication in the journal.

How to Cite

Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults. (1998). Elektronika Ir Elektrotechnika, 18(5). https://eejournal.ktu.lt/index.php/elt/article/view/16035