On Delay Test Generation for Non-scan Sequential Circuits at Functional Level

Authors

  • E. Bareisa
  • V. Jusas
  • K. Motiejunas
  • R. Seinauskas

DOI:

https://doi.org/10.5755/j01.eee.109.3.173

Abstract

Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. Bibl. 13, tabl. 4 (in English; abstracts in English and Lithuanian).

http://dx.doi.org/10.5755/j01.eee.109.3.173

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Published

2011-03-07

How to Cite

Bareisa, E., Jusas, V., Motiejunas, K., & Seinauskas, R. (2011). On Delay Test Generation for Non-scan Sequential Circuits at Functional Level. Elektronika Ir Elektrotechnika, 109(3), 67-70. https://doi.org/10.5755/j01.eee.109.3.173

Issue

Vol. 109 No. 3 (2011)

Section

ELECTRONICS

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