An Investigation of Possibilities of Improving Random Test Generation for Non-scan Sequential Circuits

Authors

  • E. Bareisa Kaunas University of Technology
  • V. Jusas Kaunas University of Technology
  • K. Motiejunas Kaunas University of Technology
  • R. Seinauskas Kaunas University of Technology

DOI:

https://doi.org/10.5755/j01.eee.114.8.685

Abstract

High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. The latest research shows that functional tests designed using random test generation exhibit good transition fault coverages. In the paper, we investigated the possibilities of improving random test generation for at-speed testing of non-scan synchronous sequential circuits. Based on research of distribution of "1" in randomly generated test pattern we suggested guidance for management of test generation process. The implementation of semi deterministic algorithms showed that the optimisation of separate steps by construction of test subsequences doesn't improve the final outcome. Ill. 2, bibl. 8, tabl. 3 (in English; abstracts in English and Lithuanian).

http://dx.doi.org/10.5755/j01.eee.114.8.685

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Published

2011-10-21

How to Cite

Bareisa, E., Jusas, V., Motiejunas, K., & Seinauskas, R. (2011). An Investigation of Possibilities of Improving Random Test Generation for Non-scan Sequential Circuits. Elektronika Ir Elektrotechnika, 114(8), 11-15. https://doi.org/10.5755/j01.eee.114.8.685

Issue

Vol. 114 No. 8 (2011)

Section

ELECTRONICS

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