The Fault Model of Programmable Logic Block

Authors

  • V. Abraitis Kaunas University of Technology
  • E. Bareiša Kaunas University of Technology

Abstract

There are presented the fault models of programmable integrated circuits in this paper, when programmable integrated circuits are configured to implement a given application. Proposed fault model can be used with traditionally automatic test sequence generators and result will be exhaustive test for programmable integrated circuits with given configuration. Model was tested using Virtex family PFGA’s. Ill. 3, bibl. 15 (in Lithuanian; summaries in Lithuanian, English and Russian).

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Published

2005-07-22

How to Cite

Abraitis, V., & Bareiša, E. (2005). The Fault Model of Programmable Logic Block. Elektronika Ir Elektrotechnika, 62(6), 48-52. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/10454

Issue

Vol. 62 No. 6 (2005)

Section

T 171 MICROELECTRONICS

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