The Fault Model of Programmable Logic Block
There are presented the fault models of programmable integrated circuits in this paper, when programmable integrated circuits are configured to implement a given application. Proposed fault model can be used with traditionally automatic test sequence generators and result will be exhaustive test for programmable integrated circuits with given configuration. Model was tested using Virtex family PFGA’s. Ill. 3, bibl. 15 (in Lithuanian; summaries in Lithuanian, English and Russian).
How to Cite
Authors retain copyright and grant the journal the right of the first publication with the paper simultaneously licensed under the Creative Commons Attribution 4.0 (CC BY 4.0) licence.
Authors are allowed to enter into separate, additional contractual arrangements for the non-exclusive distribution of the paper published in the journal with an acknowledgement of the initial publication in the journal.
Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights, Articles 4-37.