The Fault Model of Programmable Logic Block
Abstract
There are presented the fault models of programmable integrated circuits in this paper, when programmable integrated circuits are configured to implement a given application. Proposed fault model can be used with traditionally automatic test sequence generators and result will be exhaustive test for programmable integrated circuits with given configuration. Model was tested using Virtex family PFGA’s. Ill. 3, bibl. 15 (in Lithuanian; summaries in Lithuanian, English and Russian).
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