LSFR and BIST based Delay Test for ASIC and FPGA

Authors

  • V. Abraitis Kaunas University of Technology
  • Ž. Tamoševičius Kaunas University of Technology

Abstract

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration. IIl. 7, bibl. 7 (in English; summaries in English, Russian, Lithuanian).

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Published

2008-08-20

How to Cite

Abraitis, V., & Tamoševičius, Ž. (2008). LSFR and BIST based Delay Test for ASIC and FPGA. Elektronika Ir Elektrotechnika, 87(7), 45-48. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/11209

Issue

Vol. 87 No. 7 (2008)

Section

T 171 MICROELECTRONICS

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