Investigation of Porous Silicon Layers as Passivation Coatings for High Voltage Silicon Devices

Abstract

The porous silicon layer as the passivation coating for high voltage devices is proposed. PS layers having different thickness and porosity were prepared and analyzed. The dependence of the thickness on the anodization time and the effect of current density and electrolyte composition on the porosity were determined and found proportional within a good range. For this reason, is proposed to etch formed electrochemical oxide with gathered impurities inside the layer. Imroved rezults could be explained of growing broader the groove. But with removing the oxidized layer collectivelly removes gathered impurities from the bulk, what couldn`t effect growing broader of the groove. A new bottom-hole-assisted approach based on a forward biased np-junction for manufacturing n-PS layer is discussed. Illumination is an optional hole-source in the fabrication of n-type PS. The bottom-hole-assisted approach can overcome the illumination-limitation and depth-limitation problems in conventional only-illumination-assisted approach. With the bottom-hole-assistance, the anodization etching is almost anisotropic. Ill. 7, bibl. 4 (in English; summaries in English, Russian and Lithuanian).