The Analysis of Quality of CMOS Technology, Covered by Silicon Nitride

Authors

  • R. Anilionis Kaunas University of Technology
  • D. Andriukaitis Kaunas University of Technology
  • T. Keršys Kaunas University of Technology

Abstract

Problems of technology LOCOS, related with oxidation time, temperature, silicon oxide layer, patterned silicon nitride in CMOS structure was researched. During LOCOS most CMOS quality depend on gate channel shortening, diffusion region separation. LOCOS CMOS mathematical models are created using program SUPREM. It is determined, that most acceptable results are received when time t=360 min., temperature T=1000ºC, SiO2 thickness = 0,02 μm., Si3N4 thickness = 0,1 μm. Ill. 10, bibl. 5 (in Lithuanian, summaries in Lithuanian, English and Russian).

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Published

2005-04-19

How to Cite

Anilionis, R., Andriukaitis, D., & Keršys, T. (2005). The Analysis of Quality of CMOS Technology, Covered by Silicon Nitride. Elektronika Ir Elektrotechnika, 60(4), 69-73. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/10411

Issue

Vol. 60 No. 4 (2005)

Section

T 171 MICROELECTRONICS

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