Strategy of CMOS IC Layout Topology Design and Verification

Authors

  • R. Beniseviciute
  • A. Lipnickas
  • G. Sadauskas
  • G. Vaitkevicius

Abstract

The paper acquaints with design of layout methodology for non standard logical elements and cells of analog cir-cuits. The authors present algorithms of automated and interactive layout design methods and verification of their electri-cal performances. There is given comparison of electrical performances and parameters of their elements of the circuits that have been designed using the mentioned methods. The design has been carried out by CADENCE system, relying on MIETEC cell library.

Published

1998-01-14

How to Cite

Beniseviciute, R., Lipnickas, A., Sadauskas, G., & Vaitkevicius, G. (1998). Strategy of CMOS IC Layout Topology Design and Verification. Elektronika Ir Elektrotechnika, 14(1). Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/15947

Issue

Vol. 14 No. 1 (1998)

Section

Articles

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