Nanotechnology Problems using VMOS, UMOS
VMOS, UMOS transistors drain and gate are formed in the groove of “V” or “U” form. Channel area is expanded, therefore VMOS and UMOS structures may be used in power chips. Using VMOS, UMOS 40% more free space is saved than using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn splice at a right depth, during all semiconductor manufacturing technological process. Analyzing influence of each technological operation on structure formation mathematical simulation with program SUPREM IV is used. VMOS and UMOS technological operation was simulated in micro and nano levels. Ill. 10, bibl. 5 (in English; summaries in English, Russian and Lithuanian).
How to Cite
The copyright for the paper in this journal is retained by the author(s) with the first publication right granted to the journal. The authors agree to the Creative Commons Attribution 4.0 (CC BY 4.0) agreement under which the paper in the Journal is licensed.
By virtue of their appearance in this open access journal, papers are free to use with proper attribution in educational and other non-commercial settings with an acknowledgement of the initial publication in the journal.