Upgrading FPGA Implementation of Isolated Word Recognition System for a Real-Time Operation

Authors

  • T. Sledevic Vilnius Gediminas Technical University
  • G. Tamulevicius Vilnius Gediminas Technical University
  • D. Navakauskas Vilnius Gediminas Technical University

DOI:

https://doi.org/10.5755/j01.eee.19.10.5907

Keywords:

Cepstral analysis, dynamic time warping, field programmable gate array, intellectual property core, isolated word recognition, linear predictive coefficients

Abstract

The article reports on the upgrading of the FPGA based isolated word recognition system for real-time tasks. All recognition system components (except some feature calculation steps) were implemented using VHDL. Some high precision calculations were implemented on soft core processor. The employed Dynamic time warping algorithm was speeded-up 2.8 times by restricting the calculated error matrix size. This enabled us to reduce the average word recognition time to 12.81 ms. Linear predictive coding, linear predictive coding cepstral and linear frequency cepstral coefficients feature analyses were investigated for 100 Lithuanian word recognition. In speaker dependent experiments linear predictive coding cepstral analysis gave the highest average recognition rate of 95 % and the highest robustness to white noise in speech. 15 dB noise level lowered average recognition rate to 86.2 %.

DOI: http://dx.doi.org/10.5755/j01.eee.19.10.5907

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Published

2013-12-10

How to Cite

Sledevic, T., Tamulevicius, G., & Navakauskas, D. (2013). Upgrading FPGA Implementation of Isolated Word Recognition System for a Real-Time Operation. Elektronika Ir Elektrotechnika, 19(10), 123-128. https://doi.org/10.5755/j01.eee.19.10.5907

Issue

Vol. 19 No. 10 (2013)

Section

SYSTEM ENGINEERING, COMPUTER TECHNOLOGY

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