Hardware Accelerated FPGA Implementation of Lithuanian Isolated Word Recognition System

Authors

  • G. Tamulevičius Institute of Mathematics and Informatics
  • V. Arminas Vilnius Gediminas Technical University
  • E. Ivanovas Vilnius Gediminas Technical University
  • D. Navakauskas Vilnius Gediminas Technical University

Abstract

Enhancement of FPGA implementation of Lithuanian isolated word recognition system is presented. Software based recognizer implementation was used as the basis for enhancement. The feature extraction (as the most time required process) and local distance calculation (as the most times performed process) were selected for hardware implementation. Reduction of recording quality of speech was selected as the way to reduce the amount of the data to analyze. Experimental testing shows correctness of made solutions. Integration of Fast Fourier Transform module reduced the recognition time by 1.6 times, and lower quality of records increased the recognition rate by 2.8 % for speaker dependent and by 4.2 % for speaker independent recognition. The overall achieved acceleration is 6 times, average time of recognition of one word is 15.7 s. Ill. 8, bibl. 14. (in English; summaries in English, Russian and Lithuanian).

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Published

2010-03-02

How to Cite

Tamulevičius, G., Arminas, V., Ivanovas, E., & Navakauskas, D. (2010). Hardware Accelerated FPGA Implementation of Lithuanian Isolated Word Recognition System. Elektronika Ir Elektrotechnika, 99(3), 57-62. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/9906

Issue

Vol. 99 No. 3 (2010)

Section

T 125 AUTOMATION, ROBOTICS

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