Implementation of an AFDX Interface with Zynq SoC Board in FPGA

Authors

  • Fernando Molina Department of Engineering, Creative Electronic Systems
  • Pablo Corral Department of Communications Engineering, University Miguel Hernandez of Elche
  • Miguel Aljaro Department of Computers Engineering, University Miguel Hernandez of Elche
  • Guillermo de Scals Department of Applied Physics, University Miguel Hernandez of Elche
  • Alberto Rodriguez Department of Communications Engineering, University Miguel Hernandez of Elche

DOI:

https://doi.org/10.5755/j01.eie.26.5.26008

Keywords:

Aerospace electronics, Aerospace simulation, AFDX, Latency measurements

Abstract

This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collaborative project called “Mission: NET@SPACE”. It was chosen by the European Commission under the Seventh Framework Program for Research (FP7) to develop an Avionics Full Duplex Switched Ethernet (AFDX) demonstrator based in FPGA. It has to be able to receive and transmit frames and enhance the robustness. The scheduling of the protocol should also be moved into the hardware, by still keeping a small footprint of the whole design. In this paper, we introduce the theory and used technologies, the project flow and development, including the decisions and milestones, to arrive at the end to the further possibilities and conclusions.

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Published

2020-10-27

How to Cite

Molina, F., Corral, P., Aljaro, M., de Scals, G., & Rodriguez, A. (2020). Implementation of an AFDX Interface with Zynq SoC Board in FPGA. Elektronika Ir Elektrotechnika, 26(5), 11-15. https://doi.org/10.5755/j01.eie.26.5.26008

Issue

Vol. 26 No. 5 (2020)

Section

ELECTRONICS

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