Modeling and Analysis of Neuro–Genetic Hybrid System on FPGA

Abstract

Simultaneous evolution of the architecture and adaptation of weights of an Artificial Neural Network is executed using Genetic Algorithm (GA) to overcome the local minima problem. Absence of learning unit simplifies the Very Large Scale Integration (VLSI) realization of evolved Neural Network (NN). Potential of the Neurohardware is tested on two benchmark circuits; Eight–bit even Parity function and nine–bit Character Recognition. Binary input facilitates the use of comparators instead of multipliers in the hidden layer neuron, reducing the hardware complexity. While evolving the parity function using GA, the number of hidden layer neuron is reduced to half, which in turn reduces the silicon area appreciably. Character Recognition Network converges faster with acceptable error. Simulated results ensure that the designed Neuro–Genetic Hybrid System is not only fast and accurate but also hardware friendly. Ill. 7, bibl. 23, tabl. 9 (in English; abstracts in English, Russian and Lithuanian).