Fast Matrix Covering in All Programmable Systems-on-Chip
Keywords:Accelerator architectures, concurrent computing, parallel processing, field programmable gate arrays, system-on-chip
AbstractThe paper suggests a technique for solving the matrix/set covering problem in all programmable systems-on-chip. A novel very fast hardware accelerator is proposed and implemented in the programmable logic (PL) of a Xilinx Zynq microchip. The accelerator is managed by software running in the processing system (ARM Cortex-A9) available on the same microchip and communicating with the PL through high-speed interfaces. The results of implementation, experiments, and comparisons demonstrate significant speedup comparing to software running in general-purpose PC and in the ARM.
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