Fast Matrix Covering in All Programmable Systems-on-Chip

Authors

  • V. Sklyarov University of Aveiro
  • I. Skliarova University of Aveiro
  • A. Rjabov Tallinn University of Technology
  • A. Sudnitson Tallinn University of Technology

DOI:

https://doi.org/10.5755/j01.eee.20.5.7116

Keywords:

Accelerator architectures, concurrent computing, parallel processing, field programmable gate arrays, system-on-chip

Abstract

The paper suggests a technique for solving the matrix/set covering problem in all programmable systems-on-chip. A novel very fast hardware accelerator is proposed and implemented in the programmable logic (PL) of a Xilinx Zynq microchip. The accelerator is managed by software running in the processing system (ARM Cortex-A9) available on the same microchip and communicating with the PL through high-speed interfaces. The results of implementation, experiments, and comparisons demonstrate significant speedup comparing to software running in general-purpose PC and in the ARM.

DOI: http://dx.doi.org/10.5755/j01.eee.20.5.7116

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Published

2014-05-13

How to Cite

Sklyarov, V., Skliarova, I., Rjabov, A., & Sudnitson, A. (2014). Fast Matrix Covering in All Programmable Systems-on-Chip. Elektronika Ir Elektrotechnika, 20(5), 150-153. https://doi.org/10.5755/j01.eee.20.5.7116

Issue

Vol. 20 No. 5 (2014)

Section

SYSTEM ENGINEERING, COMPUTER TECHNOLOGY

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