Design of a Linear-in-dB Power Detector in 65nm CMOS Technology
DOI:
https://doi.org/10.5755/j01.eee.19.10.5902Keywords:
Dynamic range, intermediate frequency, logarithmic amplifier, power detector, radio frequencyAbstract
In this work, design and simulation results of a linear-in-dB power detector are presented. The power detector can be used in integrated wireless communication devices for received or transmitted intermediate frequency (IF) signal power monitoring and control, local oscillator (LO) leakage detection. The whole detector block is composed of a mixer, amplifier and IF logarithmic amplifier to achieve linear-in-dB power detection. Design and simulation verification was performed using Cadence software package. The proposed integrated circuit in 65 nm CMOS technology achieves a 74 dB dynamic range, while consuming 24 mW from 1,2 V power supply.Downloads
Published
2013-12-10
Issue
Section
MICRO-, NANOELECTRONICS
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How to Cite
Design of a Linear-in-dB Power Detector in 65nm CMOS Technology. (2013). Elektronika Ir Elektrotechnika, 19(10), 91-94. https://doi.org/10.5755/j01.eee.19.10.5902
