Verification of Initialization Sequences for Sequential Circuits

Authors

  • K. Morkunas Kaunas University of Technology
  • R. Seinauskas Kaunas University of Technology

DOI:

https://doi.org/10.5755/j01.eee.112.6.446

Abstract

This article suggests an approach for verification of initializing sequences. Such sequences were discovered using circuit emulating software prototypes. Software prototypes operate using bivalent logics (0 and 1), while hardware testing employs ternary logic (0, 1 and X). Experimental results show, that validation using ternary logic is too strict, labeling good initializing sequences as bad ones. Experimental results are based on ISCAS'89 benchmark. Ill. 1, bibl. 12, tabl. 3 (in English; abstracts in English and Lithuanian).

http://dx.doi.org/10.5755/j01.eee.112.6.446

Downloads

Published

2011-06-08

Issue

Vol. 112 No. 6 (2011)

Section

ELECTRONICS

License

The copyright for the paper in this journal is retained by the author(s) with the first publication right granted to the journal. The authors agree to the Creative Commons Attribution 4.0 (CC BY 4.0) agreement under which the paper in the Journal is licensed.

By virtue of their appearance in this open access journal, papers are free to use with proper attribution in educational and other non-commercial settings with an acknowledgement of the initial publication in the journal.

How to Cite

Verification of Initialization Sequences for Sequential Circuits. (2011). Elektronika Ir Elektrotechnika, 112(6), 61-64. https://doi.org/10.5755/j01.eee.112.6.446

Most read articles by the same author(s)

<< < 1 2