A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

Authors

  • Jakob K. Toft Institute of Electrical Engineering, Technical University of Denmark, Denmark
  • Ivan H. H. Jorgensen Institute of Electrical Engineering, Technical University of Denmark, Denmark https://orcid.org/0000-0002-5759-3631

DOI:

https://doi.org/10.5755/j02.eie.28852

Keywords:

Charge pumps, High-voltage techniques, Microelectromechanical systems, Microphones, Silicon-on-Insulator

Abstract

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

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Published

2021-08-02

How to Cite

Toft, J. K., & Jorgensen, I. H. H. (2021). A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process. Elektronika Ir Elektrotechnika, 1(1). https://doi.org/10.5755/j02.eie.28852

Issue

Section

MICRO-, NANOELECTRONICS