On DC Errors in Translinear Frequency Multipliers
In this paper we discuss some circuit solution intended to eliminate or to reduce the DC errors occurring in some new high bandwidth translinear frequency multipliers. Errors arise as a result of the circuit’s topology or/and of the non-ideal devices behavior. All the proposed solutions refer to a particular frequency tripler circuit and leads to significant reduction the output-offset current of a to values very close to zero. Ill. 9, bibl. 8 (in English; Summaries in English, Russian, Lithuanian).
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