NoCs Design for Verification

Authors

  • V. Hahanov Kharkov National University of Radio Electronics
  • O. Yegorov Kharkov National University of Radio Electronics
  • K. Mostova Kharkov National University of Radio Electronics

Abstract

To deploy high performance computing on a chip requires to place the number of the processors in networks on chip (NoC). To fulfill growing market demands number of processors and other IPs on a chip is also increases. Because of that general purpose bus is not efficient to provide communication between IPs and on a chip. In the article there are presented variety of NoC communication architectures and verification approaches on the basis of the hardware assertions. There are proposed design for verification approach, that will allow to use distributed with IP verification routines to ease system level validation. Ill. 10, bibl. 10 (in English; summaries in English, Russian and Lithuanian).

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Published

2007-03-19

How to Cite

Hahanov, V., Yegorov, O., & Mostova, K. (2007). NoCs Design for Verification. Elektronika Ir Elektrotechnika, 75(3), 45-48. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/10470

Issue

Vol. 75 No. 3 (2007)

Section

T 121 SIGNAL TECHNOLOGY

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