Parallel and Pipelined Hardware Implementation of Radar Signal Processing for an FMCW Multi-channel Radar

Eugin Hyun

Abstract


Ramp-sequence based frequency modulated continuous wave (FMCW) radar is effective in detecting the range and velocity of a target. However, because the target detection algorithm is based on a two-step fast Fourier transform (FFT) over several pulse-repetition intervals (PRIs), a significant amount of data must be processed in order to detect the range and velocity of the target. In specific cases, when multiple channels must be supported in order to estimate the angle position of a target, even more hardware resources and memory, as well as longer processing times, are required. In this paper, a field programmable gate array (FPGA) based radar detection algorithm with a parallel and pipelined architecture is implemented in order to support the multi-channel processing of the algorithm, which includes range and Doppler processing, digital beam forming (DBF), and constant false alarm rate (CFAR) detection. In order to effectively support the parallel and pipelined architecture, we propose a data-routing-schemed DBF and fine-grained DBF architecture. The results from implementation of the proposed hardware resources and processing times are also presented. The implemented radar sensor is installed on an experimental vehicle and is demonstrated in the field.

DOI: http://dx.doi.org/10.5755/j01.eee.21.2.7606


Keywords


FMCW radar, vehicle radar, FPGA implementation, pipelining, parallel, detection algorithm

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Print ISSN: 1392-1215
Online ISSN: 2029-5731