Hardware Acceleration of Sparse Support Vector Machines for Edge Computing

  • Vuk Vranjkovic Department of Power, Electronic and Telecommunication Engineering, Faculty of Technical Sciences, University of Novi Sad
  • Rastislav Struharik Department of Power, Electronic and Telecommunication Engineering, Faculty of Technical Sciences, University of Novi Sad
Keywords: Support vector machines, Hardware accelerator architectures, Edge computing

Abstract

In this paper, a hardware accelerator for sparse support vector machines (SVM) is proposed. We believe that the proposed accelerator is the first accelerator of this kind. The accelerator is designed for use in field programmable gate arrays (FPGA) systems. Additionally, a novel algorithm for the pruning of SVM models is developed. The pruned SVM model has a smaller memory footprint and can be processed faster compared to dense SVM models. In the systems with memory throughput, compute or power constraints, such as edge computing, this can be a big advantage. The experiments on several standard datasets are conducted, which aim is to compare the efficiency of the proposed architecture and the developed algorithm to the existing solutions. The results of the experiments reveal that the proposed hardware architecture and SVM pruning algorithm has superior characteristics in comparison to the previous work in the field. A memory reduction from 3 % to 85 % is achieved, with a speed-up in a range from 1.17 to 7.92.

Published
2020-06-27
How to Cite
Vranjkovic, V., & Struharik, R. (2020). Hardware Acceleration of Sparse Support Vector Machines for Edge Computing. Elektronika Ir Elektrotechnika, 26(3), 42-53. https://doi.org/10.5755/j01.eie.26.3.25796
Section
ELECTRONICS

Funding data