Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Jun Luo, Qijun Huang, Hongwei Luo, Yue Zhi, Xiaoqiang Wang

Abstract


Inverse square root has played an important role in Cholesky decomposition, which devoted to hardware efficient compressed sensing. However, the performance is usually limited by the trade-off between throughput and precision. This paper presents hardware implementation of fixed-point single iterated multiplicative inverse square root. Multiple piecewise linear approximation in softly nonlinear range is used to compute the initial value. Single iterated Newton-Raphson method is employed to obtain high precision. Multiple constants multiplication technique is proposed to achieve high throughput. The combination of these techniques yields high performance in terms of throughput and precision. It obtains more than 70 % of throughput improvement and almost 100 × higher precision over the inverse square root Intellectual Property (IP) from Altera. In addition, Cholesky decomposition has been presented to validate the proposed architecture, which shows that 42 % of throughput improvement is achieved compared with the IP.

DOI: http://dx.doi.org/10.5755/j01.eie.23.4.18717


Keywords


Digital circuits; fixed-point arithmetic; piecewise linear approximation; hardware

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Print ISSN: 1392-1215
Online ISSN: 2029-5731