FPGA based Packet Splitter Implementation Using Mixed Design Flow
Design and development of a FPGA based packet splitter using Handle–C DK4 design suite is reported. A mixed design flow comprising of the integration of tools from third party has been adopted for the simulation, testing, debugging and generation of the RTL model. The reported packet splitter core has lot of potential applications in passive monitoring of the networking setup, security appliances etc. Ill. 2, bibl. 8 (in English; summaries in English, Russian and Lithuanian).
Authors retain copyright and grant the journal the right of the first publication with the paper simultaneously licensed under the Creative Commons Attribution 4.0 (CC BY 4.0) licence.
Authors are allowed to enter into separate, additional contractual arrangements for the non-exclusive distribution of the paper published in the journal with an acknowledgement of the initial publication in the journal.
Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights, Articles 4-37.