Verifiable Template Development for HDL- Descriptions

  • Y. Syrevitch KhNURE
  • D. Zinchenko KhNURE

Abstract

Classification of digital devices by types of their language descriptions is introduced. Also, a template of HDL-model of digital device, which will fit verification objectives in a case of using path sensitization methods, is considered. The proposed strategy starts from origin HDL-model transformation into a graph model, which is a composition of two graphs. To identify all functional elements in an informational graph it is necessary and enough to activate all paths in a graph which cover it, starting from the 1st rank to graph outputs or control points. Usage of a template allows building a graph model of HDL-description and further verification easier. Adjustments of path sensitization verification strategy are done. Dependence of test length from the type of testing for S27, КР1804ВС1, and В06 benchmarks is analyzed. Ill. 1, bibl. 7 (in English; summaries in English, Russian and Lithuanian).

Published
2007-03-19
How to Cite
Syrevitch, Y., & Zinchenko, D. (2007). Verifiable Template Development for HDL- Descriptions. Elektronika Ir Elektrotechnika, 75(3), 53-56. Retrieved from http://eejournal.ktu.lt/index.php/elt/article/view/10471
Section
T 121 SIGNAL TECHNOLOGY