Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern

Authors

  • Rimantas Seinauskas Kaunas university of Technology
  • Ramunas Cvirka Kaunas University of Technology
  • Greta Rudzioniene Kaunas University of Technology

DOI:

https://doi.org/10.5755/j01.eee.21.3.5774

Keywords:

fault simulation, testing, design, hardware

Abstract

A new fault simulation procedure is suggested. Procedure provides fault detection of individual test patterns at the beginning. In this way, most faults are detected quickly. The remaining faults are analyzed by conventional means in respect of a sequence of test patterns. Creation of individual fault lists of test patterns allows speeding up the fault simulation. Fault simulation acceleration increases with circuit size and test coverage.

DOI: http://dx.doi.org/10.5755/j01.eee.21.3.5774

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Published

2015-05-28

How to Cite

Seinauskas, R., Cvirka, R., & Rudzioniene, G. (2015). Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern. Elektronika Ir Elektrotechnika, 21(3), 62-65. https://doi.org/10.5755/j01.eee.21.3.5774

Issue

Vol. 21 No. 3 (2015)

Section

SYSTEM ENGINEERING, COMPUTER TECHNOLOGY

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