Analysis of Possibilities of Faults Diagnostic by CMOS Integrated Circuits
AbstractThe new tendencies of circuit fabrication conditioned the investigation of new design methods. One from such trends is the technology with standardized minimal line width. Technologies of such type are widely used for the CMOS design. The libraries of basic elements are formed for the certain technology. The problem of logical fault localization in accordance with transistor level faults is analysed. The fault diagnostic program Verifault is used to simulate logical circuits. The transistor level faults are simulated by programs Spice and Verilog Switch-XL, Switch-RC, and Switch-R. The possibilities of fault simulation with XL, R and RC switches level are researched. The comparable analizis of fault localization is carried out, simulating at the level of logical elements, transistors and switches. The sequential and combinational circuits of ES2 and Mietec technological library were investigated.
How to Cite
The copyright for the paper in this journal is retained by the author(s) with the first publication right granted to the journal. The authors agree to the Creative Commons Attribution 4.0 (CC BY 4.0) agreement under which the paper in the Journal is licensed.
By virtue of their appearance in this open access journal, papers are free to use with proper attribution in educational and other non-commercial settings with an acknowledgement of the initial publication in the journal.