Propagation Delay Model of Gallium Arsenyde Emitter-Coupled Logic Circuits
AbstractThere was analysed the possibility of estimation of rough propagation delay time of GaAs emitter-coupled logic (ECL) circuits. Comparable analysis of gallium arsenide and silicon transistor constructions, technologies and models was carried out. For PSPICE modelling were chosen parameters of GaAs heterostructure bipolar transistors. Reconstructed model of propagation delay of similar silicon integrated circuits, which has been worked out before, was proposed for estimation of propagation delay time of tree type GaAs ECL basic cells. The suitableness of methodics for estimation of propagation delay time of the proposed GaAs ECL basic cells is checked by modelling these circuits by means of PSPICE software for analysis of electronic circuits.
How to Cite
Authors retain copyright and grant the journal the right of the first publication with the paper simultaneously licensed under the Creative Commons Attribution 4.0 (CC BY 4.0) licence.
Authors are allowed to enter into separate, additional contractual arrangements for the non-exclusive distribution of the paper published in the journal with an acknowledgement of the initial publication in the journal.
Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights, Articles 4-37.