Propagation Delay Model of Gallium Arsenyde Emitter-Coupled Logic Circuits

Abstract

There was analysed the possibility of estimation of rough propagation delay time of GaAs emitter-coupled logic (ECL) circuits. Comparable analysis of gallium arsenide and silicon transistor constructions, technologies and models was carried out. For PSPICE modelling were chosen parameters of GaAs heterostructure bipolar transistors. Reconstructed model of propagation delay of similar silicon integrated circuits, which has been worked out before, was proposed for estimation of propagation delay time of tree type GaAs ECL basic cells. The suitableness of methodics for estimation of propagation delay time of the proposed GaAs ECL basic cells is checked by modelling these circuits by means of PSPICE software for analysis of electronic circuits.