Enhanced Hardware Efficient FFT Processor Based On Adaptive Recoding CORDIC

Authors

  • Jianfeng Zhang National University of Defense Technology
  • Hengzhu Liu National University of Defense Technology
  • Ting Chen National University of Defense Technology
  • dongpei liu
  • Botao Zhang National University of Defense Technology

DOI:

https://doi.org/10.5755/j01.eee.19.4.1422

Keywords:

Fast Fourier transforms, CORDIC, bit error precision, signal to noise ratio

Abstract

In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the bit error precision (BEP) of which is improved to 14th. Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4us.

DOI: http://dx.doi.org/10.5755/j01.eee.19.4.1422

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Published

2013-03-28

How to Cite

Zhang, J., Liu, H., Chen, T., liu, dongpei, & Zhang, B. (2013). Enhanced Hardware Efficient FFT Processor Based On Adaptive Recoding CORDIC. Elektronika Ir Elektrotechnika, 19(4), 97-103. https://doi.org/10.5755/j01.eee.19.4.1422

Issue

Vol. 19 No. 4 (2013)

Section

TELECOMMUNICATIONS ENGINEERING

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