Implementation Analysis of Matrix Power Cipher in Embedded Systems
AbstractIn this paper we present a theoretical implementation analysis of new matrix power cipher in embedded systems. This cipher is based on the matrix power function. This allows achieving required security and efficiency while minimizing the number of rounds. In this paper we briefly overview the matrix power and the whole cipher, discuss the security assumptions and specify the limits of security parameters. The speed of the cipher was estimated by counting operations considering the usage of look-up tables and realization in 8-bits AVR microcontrollers. Theoretical speed of the matrix power cipher was compared with the fastest known AES-128 implementations. Our cipher performs faster than AES-128 when encryption and decryption are considered together. Bibl. 11, tabl. 1 (in English; abstracts in English and Lithuanian).
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