Runtime Bitstream Relocation based Intrinsic Evolvable System

Kaifeng Zhang, Huanzhang Lu, Shanzhu Xiao, Weidong Hu

Abstract


Earlier evolvable hardware (EHW) platforms suffer from major drawbacks such as high area and delay overheads, high configuration memory overhead, low configuration speed and lack of flexibility. In this paper, we propose an intrinsic evolvable system on dynamic partial reconfigurable (DPR) platform using bitstream relocation technique to address these limitations. This relieves the overhead of configuration memory required to save the partial bistream (PB). In addition, the data transfer time between the configuration memory and the field programmable gate array (FPGA) is also reduced, which leads to a relatively high configuration speed. We implemented the proposed evolvable system using an FPGA board with an application of an adaptive finite impulse response (FIR) filter. The experimental result shows that the proposed system can achieve 116 × configuration speedup and 85 % configuration memory saving.

DOI: http://dx.doi.org/10.5755/j01.eee.20.6.4878


Keywords


Evolvable hardware; dynamic partial reconfiguration; bitstream relocation; bitstream compression

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Print ISSN: 1392-1215
Online ISSN: 2029-5731