Hardware Efficient Reciprocal Using Second Order Harmonized Parabolic Synthesis and Squaring Shrunk Method

  • Jun Luo
  • Hongwei Luo
  • Yue Zhi
  • Xiaoqiang Wang
  • Hongfeng Lv
  • Ming Dang
Keywords: Digital integrated circuits, Parallel architectures, High performance computing, Field programmable gate arrays.


In applications as in wireless communication, computer graphics and digital signal processing, a massive of complex matrix operations is often performed. Reciprocal is computed in large quantities in these matrix operations. To obtain high performance, efficient algorithm and hardware architecture are important in terms of low cost, low computation time and high precision. Second order first sub-function and squaring shrunk method have been proposed to build efficient hardware architecture for reciprocal using field programmable gate array. Second order first sub-function in harmonized parabolic synthesis is presented to improve the approximating precision and decrease the memory usage at the cost of additional multipliers. To further reduce the complexity, squaring shrunk method is proposed to decrease the expensive cost of multipliers. The combination of these techniques yields good performance trade-off. Precision simulation and hardware implementation result has shown that hardware reciprocal of high precision, low memory and low multiplier usage has been obtained compared to traditional first order first sub-function harmonized parabolic synthesis method.

DOI: http://dx.doi.org/10.5755/j01.eie.24.2.20635