Specific Features of Faults of Combinational CMOS Circuits
This research work investigated a problem of application of transistors level fault model and its adequacy to faults at logical level of circuit. There were elaborated the faults at logical and at functional level using the software package CADENCE. The faults at transistors level were simulated by software package PSPICE. There were done the comparative results of fault simulation and fault coverage at transistors level and at logical level of CMOS circuit. Ill. 3, bibl. 4 (in English; summaries in English, Russian and Lithuanian,).
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