Beniseviciute R, Lipnickas A, Sadauskas G, Vaitkevicius G. Strategy of CMOS IC Layout Topology Design and Verification. ELEKTRON ELEKTROTECH [Internet]. 1998 Jan. 14 [cited 2026 Jan. 22];14(1). Available from: https://eejournal.ktu.lt/index.php/elt/article/view/15947