On Delay Test Generation for Non-scan Sequential Circuits at Functional Level. Elektronika ir Elektrotechnika, [S. l.], v. 109, n. 3, p. 67–70, 2011. DOI: 10.5755/j01.eee.109.3.173. Disponível em: https://eejournal.ktu.lt/index.php/elt/article/view/173.. Acesso em: 5 dec. 2025.