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Beniseviciute R, Butkus L, Seinauskas R. Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults. ELEKTRON ELEKTROTECH. 1998;18(5). Accessed February 8, 2026. https://eejournal.ktu.lt/index.php/elt/article/view/16035