Bareiša E, Bieliauskas P, Jusas V, Targamadzė A, Motiejūnas L, Šeinauskas R. Factor of Randomness in Functional Delay Fault Test Generation for Full Scan Circuits. ELEKTRON ELEKTROTECH [Internet]. 2010Oct.29 [cited 2024Apr.26];105(9):39-42. Available from: https://eejournal.ktu.lt/index.php/elt/article/view/9165