V. Kašauskas, R. Anilionis, and D. Eidukas, “Simulation of the MOS Transistors Structures Channel Technological Problems”, ELEKTRON ELEKTROTECH, vol. 106, no. 10, pp. 139–142, Nov. 2010, Accessed: Feb. 07, 2026. [Online]. Available: https://eejournal.ktu.lt/index.php/elt/article/view/9144