Beniseviciute, R., Lipnickas, A., Sadauskas, G. and Vaitkevicius, G. (1998) “Strategy of CMOS IC Layout Topology Design and Verification”, Elektronika ir Elektrotechnika, 14(1). Available at: https://eejournal.ktu.lt/index.php/elt/article/view/15947 (Accessed: 21November2024).