SYREVITCH, Y.; ZINCHENKO, D. Verifiable Template Development for HDL- Descriptions. Elektronika ir Elektrotechnika, [S. l.], v. 75, n. 3, p. 53-56, 2007. Disponível em: https://eejournal.ktu.lt/index.php/elt/article/view/10471. Acesso em: 27 nov. 2020.