TEMICH, S. .; GOLONEK, T. .; GRZECHCA, D. . Design an Identification Function to Reduce the Computational Resources on the Testing Process of an Analog Electronic Circuit. Elektronika ir Elektrotechnika, [S. l.], v. 25, n. 3, p. 25-33, 2019. DOI: 10.5755/j01.eie.25.3.23672. Disponível em: https://eejournal.ktu.lt/index.php/elt/article/view/23672. Acesso em: 23 nov. 2024.