SLEDEVIC, T.; NAVAKAUSKAS, D. FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron. Elektronika ir Elektrotechnika, [S. l.], v. 22, n. 2, p. 92-95, 2016. DOI: 10.5755/j01.eie.22.2.14598. Disponível em: https://eejournal.ktu.lt/index.php/elt/article/view/14598. Acesso em: 21 nov. 2024.