Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics. Elektronika ir Elektrotechnika, [S. l.], v. 19, n. 10, p. 81–86, 2013. DOI: 10.5755/j01.eee.19.10.2464. Disponível em: https://eejournal.ktu.lt/index.php/elt/article/view/2464.. Acesso em: 5 dec. 2025.