Optimized Design of SoC-based Control System for Multi-axis Drive

This study presents an optimized system-on-chip (SoC) based multi-axis control system for permanent magnet synchronous motor (PMSM). The multi-axis control system becomes considerably complex with increasing controlled axes and complicated control algorithms. This paper aims to provide a balanced design considering control performance, hardware constrains and feasibility. To cope with this problem, the system design is optimized by using pipeline and time division multiplexing technology. Due to the optimized architecture and the computation capability of SoC, the performance of the whole system can be preserved. To demonstrate this, a SoC implementation of the control system is presented and comprehensively analyzed. Herein, the vector control in the current loop is explained and an anti-windup proportional-integral (PI) controller is adopted in the speed loop. The sampling frequencies of the current loop and the speed loop are 16 KHz and 4 KHz respectively. Consequently, the execution time is several microseconds with reasonable consumed resources. Experimental results are shown to prove the efficiency of the proposed SoC-based solution. DOI: http://dx.doi.org/10.5755/j01.eee.20.7.4848

1 Abstract-This study presents an optimized system-on-chip (SoC) based multi-axis control system for permanent magnet synchronous motor (PMSM).The multi-axis control system becomes considerably complex with increasing controlled axes and complicated control algorithms.This paper aims to provide a balanced design considering control performance, hardware constrains and feasibility.To cope with this problem, the system design is optimized by using pipeline and time division multiplexing technology.Due to the optimized architecture and the computation capability of SoC, the performance of the whole system can be preserved.To demonstrate this, a SoC implementation of the control system is presented and comprehensively analyzed.Herein, the vector control in the current loop is explained and an anti-windup proportional-integral (PI) controller is adopted in the speed loop.The sampling frequencies of the current loop and the speed loop are 16 KHz and 4 KHz respectively.Consequently, the execution time is several microseconds with reasonable consumed resources.Experimental results are shown to prove the efficiency of the proposed SoC-based solution.

I. INTRODUCTION
For the fast progress of very large scale integration (VLSI) and electronic design automation (EDA), system-on-chip (SoC) technology is getting widely used due to its efficiency in term of control performance, cost, power consumption and development time in industrial control systems.The main advantages of SoC-based solution are the shorter execution time than fully software-solution and the less complicated development than fully hardware-solution.
Especially in the field of motor drives, such as permanent magnet synchronous motor (PMSM) [1]- [3] and brushless DC motor (BLDC) [4], [5] drives which have widely used in industrial control systems, the SoC-based solution is more efficient than the digital signal processor (DSP) based solution [6]- [8].In order to reduce system cost and power consumption, the hardware/software co-design methodology has created an opportunity to make optimal SoC designs for increasingly sophisticated control systems [9], [10].
The research of SoC-based system for PMSM has become a popular field, which focuses on current control [11]- [14] speed control [10], [15], sensorless control [16], [17], multi-axis system [18], [19], etc.Compared with the network-based solution [20], [21], the SoC-based solution is simple, real-time and low-cost for small and medium-sized multi-axis control systems.The SoC environment can be constructed inside field programmable gate array (FPGA) architectures with embedded hard processor cores such as PowerPC or ARM, soft processor cores such as Nios II or Micro-blaze and some other dedicated blocks such as random access memory (RAM) [22], [23].
Nowadays, more and more researchers have focused on implementation of controllers based on SoC and FPGA for robot and computer numerical control machine tool (CNC) applications.Shao et al. [24] presented a motion control architecture using FPGA for servo control and DSP for trajectory generation and dynamic compensation.Cho et al. [25] presented the implementation of a FPGA-based motion controller including interpolation, kinematics calculation, servo control, etc. Martinez-Prado et al. [26] described the implementation of a multi-axis motion controller for robotic applications on low-cost FPGA.Astarloa et al. [27] presented a SoC-based multi-axis system where the intensive operations and the trajectory computation are realized by hardware and software respectively.Chen et al. [28] developed a SoC-based CNC system integrating a general-purpose processor, a motion control core, an axis control core, etc.But motor drive modules cannot be fully realized in the above solutions.
Ying-Shieh Kung et al. [7], [29] developed SoC-based motion control systems for different applications.In these solutions, current vector controller for PMSMs and interfaces can be realized by hardware and the other function modules such as position/speed controller and trajectory calculation can be realized by software.However, the hardware characteristic of parallelism cannot be fully utilized in most of the solutions for multi-axis systems.Consequently, the resource consumption and the execution time cannot be optimized effectively.These solutions lead to great negative effects with increasing controlled axes and complicated control algorithms.In order to exploit the advantages, an optimized SoC-based architecture for multi-axis drive is presented in Fig. 1, where the multi-axis timing schedule module is developed by hardware using pipeline and time division multiplexing technology.This solution can be implemented in both high-performance devices and low-cost devices.Furthermore, we adopt the new-generation SoC Zynq-7000 to develop the whole system with embedded hard processor cores, which contains dual ARM Cortex-A9 processing system including hardened memory controllers and peripherals.

II. SYSTEM DESCRIPTION OF MULTI-AXIS DRIVE AND ITS OPTIMIZED DESIGN
The architecture of the SoC-based control system for the multi-axis drive is illustrated in Fig. 1.The current vector controller for PMSM is developed by hardware.The anti-windup proportional-integral (PI) speed controller is developed by software in the embedded processor.Fig. 1 presents four motor drives in the proposed system and it is quite easy to be reconfigured for more motor drives with a little additional resource.

A. Mathematical Model of Permanent Magnet Synchronous Motor
The typical mathematical model of a PMSM can be expressed by: where id and iq are the d-axis and q-axis currents; ud and uq are the d-axis and q-axis voltages; Ld and Lq are the d-axis and q-axis inductances; Rs are the stator winding resistance; ωe is the electrical angular speed; λf is the permanent magnet flux linkage.
The current vector control method is used in the proposed PMSM drive.The PMSM will be decoupled and controlled like a DC motor when the id is controlled to 0. Hence, the electromagnetic torque can be described according to the following equations: Finally, the dynamic equation of PMSM drive system can be written as below where Te is the motor torque, Kt is the torque constant, P is the number of PMSM poles, TL is the load torque, Jm is the inertial value, ωr is the rotor speed, and Bm is the damping ratio.
The current loop of the PMSM drives shown in Fig. 1 is implemented by hardware, including current controller module (with two PI controllers), abc-dq transformation (with Clarke module and Park module), dq-abc transformation (with inverse Park module and inverse Clarke module), space vector pulse width modulation (SVPWM) module, quadrature encoded pulses (QEP) module, analog to digital converter (ADC) interface, and multi-axis timing schedule module.

B. Algorithm Modular Description and Partition
The aim of the algorithm modular partition, which was summarized in [9], is to decompose the design into functional modules with different levels of granularity.The functional modules consist of coordinate transformation, current controller and SVPWM, which are appropriate for the optimized multi-axis drive design.
The coordination transformation in Fig. 1 includes Clarke, inverse Clarke, Park, inverse Park, which can be obtained by Park: cos sin , sin cos Inverse Park: cos sin , sin cos Inverse Clark: where ia , ib and ic are the stator currents respectively; iα and iβ are the α-axis and β-axis currents; uα and uβ are the α-axis and β-axis voltages; ua , ub and uc are the stator voltages.In Fig. 1, two digital PI controllers are presented in the current loop and described below: where id * and iq * are the current commands of d-axis and q-axis; ed and eq represent the d-axis current error and q-axis current error; Kcdp, Kcqp, Kcdi and Kcqi are the P control gain and I control gain of d-axis and q-axis current controller respectively; Tc is the sample time of the current controller.Furthermore, an anti-windup strategy is presented according to the following equations: ( 1), ( ( ) ), max with: where Id and Iq denote the integrator output of the proposed d-axis and q-axis PI controllers; udmax and uqmax are the limit value of the d-axis and q-axis PI controllers output; umax is the square sum limit value of the d-axis and q-axis PI controllers output.

C. Anti-windup PI Speed Controller
The tracking back calculation is widely used to avoid integrator windup [30], [31].The anti-windup PI speed controller proposed in the literature is shown in Fig. 2, where Ksp, Ksi and Ksa denote the P control gain, I control gain and the anti-windup gain respectively; isp and isi are the P control output and I control output; ωr * and ωr are the speed commend and rotor speed; psmax and omax are the output limits of P control and PI control.
The difference es between the controller output and the saturated output is used to reduce the integrator input.The tracking back calculation is not to reset the integrator but to regulate the integrator input dynamically.
Once isp exceeds the saturation limit, the desaturation of the tracking back calculation is slow and system performance is negatively affected.
Hence, the integrator is reset in one sampling period if isp is saturated.And the sample time Ts of the PI controller is determined according to the sampling frequency of the speed loop.
The proposed anti-windup PI controller is described as follows: ,

D. Optimized Multi-axis Drive Design
In order to optimize the multi-axis system design, pipeline and time division multiplexing technology are used here on the above algorithm modular partition.Compared with the single axis drive, the multi-axis drive is reliable with a little additional time and resource consumption.
Supposing the number of controlled axes is n, the multi-axis timing schedule module is utilized to complete the computation process from the No. 0 axis to the No. n-1 axis in order.And the computations, including Clarke transformation, Park transformation, current control algorithm, inverse Park transformation, inverse Clarke transformation and SVPWM, must be completed in order.The detailed multi-axis timing schedule is shown in Fig. 3. Considering the execution time of the modules is not identical, the activating conditions of each module for the No. j axis are 1) the last module for the No. j has finished and 2) this module for No. j-1 has also finished.The No. j axis denotes the motor to be controlled.The schedule scheme is summarized as follows.
Step 1: If the Clarke module for the No. j-1 axis finishes, the Clarke module for the No. j axis is activated.
Step 2: The Park module for the No. j axis is activated if 1) the Clarke module for the No. j axis finishes and 2) the Park module for the No. j-1 finishes.
Step 3: The current controller module for the No. j axis is activated if 1) the Park module for the No. j axis finishes and 2) the current controller module for the No. j-1 axis finishes.
Step 4: The inverse Park module for the No. j axis is activated if 1) the current controller module for the No. j axis finishes and 2) the inverse Park module for the No. j-1 axis finishes.
Step The inverse Clarke module for the No. j axis is activated if 1) the inverse Park module for the No. axis finishes and 2) the inverse Clarke module for No. j-1 finishes.
Step 6: The SVPWM module for the No. j axis is activated if 1) the inverse Clarke module for the No. j axis finishes and 2) the SVPWM module for No. j-1 finishes.In addition, the multi-axis selector in Fig. 1 is used to transmit electrical angles and current signals to appropriate modules.Actually, the multi-axis timing schedule module and the multi-axis selector are auxiliary to each other.

A. Development and Analysis of the Hardware Solution
Considering performance, flexibility, power and cost, a standard module is developed.Finite state machine (FSM) method is efficient to reduce the consumed hardware resource for PMSM drive, which has been proved in [32].Also it is advantageous for the optimized multi-axis drive design.Therefore, a standard FSM module is presented in Fig. 4, which has also been adopted in [13].Figure 5  Figure 6 shows the hardware realization of the multi-axis drive.The time schedule module generates axis signals, including axis_clarke, axis_park, axis_controller and axis_ipark, to control the algorithm data with the multi-axis selector.
In Fig. 7, the sequential timing diagram of the hardware solution is presented.The QEP module is synchronized with the encoders.The ADC interface is managed by the current loop start signal Start with a sampling period tc equal to 62.5 μs.The proposed hardware solution is realized in Xilinx Zynq-7000: XC7Z020, coded in Verilog hardware description language (Verilog HDL).Zynq-7000: XC7Z020 is based on the Xilinx all programmable SoC architecture that combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system (PS) with Xilinx 7 series programmable logic (PL) containing 85120 logic cells, 220 programmable DSP slices and 560KB block ram [33].The Zynq-7000 device integrates advanced extensible interface (AXI) for high throughput data transfer between PS and PL.In this work, the execution time of the communication PL-to-PS tl fixed to 1.78 μs is equal to the execution time of the communication PS-to-PL tp.In Table I, the consumed resources of a 4-axis drive are obtained for 16-bits length and Q15 fixed-point format.In Table II, the hardware is implemented with a 90 MHz clock frequency in Zynq-7000.The execution time depending on the clock frequency has been calculated using the following equation where tex is the execution time and fclk is the clock frequency.Note that the chosen ADC device in this paper is AD7265 which contains dual 12-bits, 3-channel ADCs and features throughput rates of up to 1 Msps.The ADC interface execution time denotes its SoC latency but not ADC device latency.
The results in Table II indicate that the execution time tex is very small compared with the sampling period tc.In Table I, the consumed resources are obtained for the designed modules and interfaces.These modules and interfaces can also be implemented in low-cost devices except the AXI.Though the considerable consumed resources are needed for the AXI implementation, the AXI average throughput is over 124 Mbps.Consequently, the chosen hardware solution is efficient for reasonable consumed resources and short execution times.

B. SoC Development and Analysis of the Multi-axis Drive
The current vector controller and the proposed speed controller for multi-axis drive are implemented in PL and PS respectively.The sampling frequency of the current loop and the speed loop is designed with 16 KHz and 4 KHz.The data type in PL and PS is Q15 and Q16 fixed-point format respectively.
Figure 8 shows the sequential timing diagram of the implemented SoC-based multi-axis drive.Once signal sampling and current loop computation finish, the data is transmitted from PL to PS with communication latency.When the communication finishes, the speed loop computation starts immediately.Also, when the communication finishes from PS to PL in order to update current controller reference, the current loop computation begins with small latency.Consequently, the system performance is preserved due to the method of optimizing system latency.

IV. EXPERIMENT AND RESULTS
Experiments were carried out on a SoC-based 4-axis prototyping control system depicted in Fig. 1.The experimental setup is presented in Fig. 9 which is composed of four PMSMs with 2500 lines incremental encoders, a Zynq-7000 SoC board, an AD conversion board and a metal oxide semiconductor field effect transistor (MOSFET) drive board.The PMSM parameters are shown in Table III.
The AD conversion board is used to convert analog signals to digital signals for the measured currents and to provide the interface between the SoC board and the MOSFET drive board.A serial interface RS232 is used to send controller commends and set system parameters from the host PC to the SoC.The experimental results are plotted by Matlab software.Also, Fig. 12 presents a step response.Figure 13 shows the current response of iq * , iq and id for Fig. 12 with id * = 0.The step response of each PMSM rotor speed is for 0 rpm-2400 rpm, 0 rpm-1800 rpm, 0 rpm-1500 rpm and 0 rpm-600 rpm at different step time 1 ms, 13 ms, 21 ms and 57 ms respectively.These results indicate the designed speed and current controllers have a good tracking performance and high control bandwidth.The SoC-based control system can be set flexibly.V. CONCLUSIONS An optimized SoC-based control system for the multi-axis drive is demonstrated in this paper.The algorithm modules have been realized efficiently by using the pipeline and time division technology.Thanks to the optimized architecture and the hardware computation capability, the execution time is very small compared with the sampling of the current loop and the total resource consumption is reasonable.The experimental results have validated the good performance of the proposed system.
The proposed design has three benefits described as follows.
1) The system parallel processing is available and efficient by hardware with the multi-axis timing schedule and the specific architecture.
2) The high performance on-chip interface AXI is used for development, supervision and control of the multi-axis system.It is more reliable and flexible than the external bus interface.
3) The system is configurable to expand to a multi-axis control system for complex applications conveniently, such as robot and CNC.

Fig. 1 .
Fig. 1.Architecture of the SoC-based control system for the multi-axis drive.
shows the timing diagram of the FSM module.The input signals are a start signal to activate the module and input data signals to receive algorithm data from the last module.The output signals are an end signal to be generated when the module finishes and output data signals to transfer algorithm data to the next module.The algorithm modules are realized with FSM including Clarke module, Park module, current controller module, inverse Park module, inverse Clarke module and SVPWM module.The multi-axis timing schedule module and the multi-axis selector manage the algorithm modules which are synchronized by the clock signal (clk).

Fig. 7 .
Fig. 7. Sequential timing diagram of the proposed hardware solution.

Figure 10 and
Figure 10 and Fig. 11 show the magnitude-frequency response and phase-frequency response.The results are obtained by an applied sinusoidal reference (with variable
Table I and Table II summarize the hardware area/time performance of the proposed solution.

TABLE I .
HARDWARE AREA PERFORMANCE OF THE PROPOSED SOLUTION.

TABLE II .
HARDWARE TIME PERFORMANCE OF THE PROPOSED SOLUTION.