A 0.49 mm 2 CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application

1 Abstract —This paper describes the implementation of low-power, low-phase-noise (PN), and robust startup tailless class-C voltage-controlled oscillator (TVCO) for 5G new radio (NR) technology. It features dual gate voltage control source biasing to generate fast startup and differential signal amplitude balancing, thus eliminating the requirement of the conventional tail current source, which introduces more parasitic capacitance that affects the oscillation frequency, phase noise, and power consumption. The TVCO is fabricated in 180 nm complementary metal-oxide semiconductor (CMOS) technology, oscillating at 2.59 GHz 5G NR carrier frequency with an output voltage swing of 1.7 V and low-phase-noise of - 122 dBc/Hz at 1 MHz offset with supply voltage headroom of 0.7 V. Without additional features added, the TVCO consumes very low-power and a small die area of 0.98 mW and 0.49 mm 2 , respectively. The achieved figure of merit (FoM) is 190.36 dBc/Hz.


I. INTRODUCTION
The 5G new radio (NR) technologies are currently the cutting-edge high-data rate wireless communication transmission system due to their low latency characteristics [1]. The frequency bands involved for 5G are divided into two different spectrums: sub-6 GHz and mmWave [2]. High-data rate transmission consumes substantial power [3]- [8]. As the developments are rapid for 5G NR radio systems, the voltage-controlled oscillator (VCO) has been identified as one of the power-hungry blocks, and research works focus on achieving optimal balance performance in terms of high energy efficiency, low-phase-noise, and operating bandwidth [9]- [19]. The inductor-capacitor (LC) VCO is a preferred solution to attain the operating bandwidth for the 5G NR radio system. Due to its powerhungry nature, operating the LC VCO in Class-C mode is Manuscript  quite prevalent [15], [16]. However, these Class-C oscillators suffer phase noise and startup due to low biasing, which was intended to reduce the VCO power consumption. Other efforts to reduce the power consumption of the VCO are near the threshold biasing mechanism [17], the use of the inversion metal-oxide semiconductor (IMOS) varactor [18], and the active load [19]. However, the trade-off between phase noise and power consumption remains eminent. The main contributor to VCO phase noise and output voltage swing is the tail current source [20]- [23]. The tail current source adds additional parasitic components to the VCO circuit besides the source coupled pair (XCP) transistors. Nevertheless, it is popular, as it ensures a balance oscillation between two differential outputs.
The functionality of low-power VCO with balanced output and fast startup is vital to protect the efficiency of the overall 5G NR transceiver system [24], [25]. Therefore, this work proposes a tailless Class-C voltage-controlled oscillator (TVCO) to reduce the phase noise and power consumption trade-off. A comprehensive analysis has been performed to determine the oscillation frequency and flicker noise, including the parasitic effects, followed by the figure of merit (FoM) calculation, which defines the trade-off between phase noise and power consumption. A dual gate voltage control source is implemented to ensure balanced output for differential amplifiers.
This paper is organized as follows. Section II describes the mode of operation with the analysis of the proposed TVCO, followed by Section III, which represents the flicker noise analysis of the proposed architecture. Next, Section IV represents the simulation and measurement results, and conclusions are drawn in Section V.

II. PRINCIPLE OF OPERATION
The TVCO schematic is illustrated in Fig. 1. It consists of a high-Q LC tuner, cross-coupled pair n-type metal-oxide semiconductor (nMOS) M 1 and M 2 , each having its respective gate controllers V C1 and V C2 . V C1 and V C2 play an essential role in ensuring fast startup. The L 1 , C var1 , and C var2 represent the resonant tank tuned under tuning voltage, V TUNE adjusted in the range of 0.1 V-1.8 V. The location of the parasitic capacitances C gd (gate-drain), Cgs (gatesource), and Cdb (drain-bulk) are also included for theoretical analysis. Without the conventional tail current source, the parasitic capacitances are reduced, thus improving the output voltage swing and reducing the phase noise of the low-power Class-C VCO.  With the aid of an external voltage source, antisymmetrical nodal analysis is performed to determine the true oscillation frequency, ω OSC, which includes parasitic capacitances. The total parasitic capacitances of the tailless XCP VCO are given as Since V 1 and -V 1 are antisymmetrical nodes, the input admittance Y IN can be computed as Figure 3 illustrates the simplified TVCO model where R and C XCP represent the real and imaginary of (2). From this, the oscillation frequency ω OSC is determined as where R and C XCP are given in (4) and (5), respectively: Inserting (4) and (5) into (3) results in the true oscillation frequency, given in (6) with f OSC, the figure of merit (FoM) of the TVCO is given as where L is the phase noise in Δf offset frequency, and P diss is the power dissipation.  Figure 4 shows the comparison of startup G m between conventional Class-C and TVCO. The TVCO has a higher G m for all three process corners than the conventional Class-C VCO due to the reduced parasitic capacitance at the gate of M 1 and M 2 .
The dual gate biasing method manoeuvres the Cgs 1,2 as such, it works as part of a low-pass filter (LPF) once integrated with resistor R 1,2 . The R 1,2 -Cgs 1,2 LPF too significantly reduces the high-frequency noise and hence contributes to fast startup. Accordingly, a balance amplitude swing is obtained.
where q is the elementary charge, D t (E F ) is the active trap density, K is the Boltzmann constant, τ 1 and τ 2 is the trapping time, and T is the temperature in Kelvin.
The 1/f noise transconductance of M 1, 2 is given as: Equation (16) reveals that the 1/f noise is highly dependent on the device size (W/L) and the gate to source voltage, V GS . Hence, in our work, we reduced the 1/f noise by lowering the V GS and increasing the device length (L) without trading off the area of the chip. Therefore, the 1/f noise is subsequently decreased, resulting in a lower flicker upconversion to 1/f 2 (20 dB/dec) and 1/f 3 (30 dB/dec), thus improving the overall phase noise performance of the TVCO. Figure 6 illustrates the simulated output waveform of conventional Class-C and TVCO, where the imbalance amplitude is triggered by uneven gate biasing to form a Class-C core operation. Class C's amplitude imbalance and distortion during the triode region generated more flicker noise. With the dual gate control aided in TVCO, a more balanced amplitude waveform and zero distortion have been produced, thus reducing the 1/f noise. The balanced signal amplitude at their zero-crossing point provides a better phase noise (PN) improvement, becoming less sensitive to injected noise than the Class-C core. IV. SIMULATION AND MEASUREMENT RESULTS Figure 7 illustrates the micrograph of the TVCO manufactured in the 180 nm radio frequency (RF) CMOS technology process that occupies the core area of 0.49 mm 2 , including the bond pads. The measurement setup of the proposed architecture is shown in Fig. 8.    Figure 10 illustrates the phase noise measured in the operating bandwidth of the TVCO. The corresponding phase noise at 2.5 GHz, 2.59 GHz, and 2.67 GHz is -122.5 dBc/Hz, -122 dBc/Hz, and -120.97 dBc/Hz, respectively. Figure 11 depicts the PN and power consumption (P DC ) of the TVCO across the tuning voltage. The highest achieved PN is -119.5 dBc/Hz with a corresponding P DC of 1.3 mW, while the lowest achieved is -122.5 dBc/Hz with a P DC of 0.17 mW. Hence, a minimum trade-off performance between PN and P DC has been achieved. The corresponding frequency across V TUNE is shown in Fig. 12. The simulated carrier frequency shows 2.53 GHz to 2.69 GHz, and the measured shows 2.5 GHz to 2.67 GHz across 0.1 V to 1.8 V tuning voltage, V TUNE . Figure 13 depicts the thermal analysis from -25 ºC to 125 ºC of the TVCO at 2.59 GHz.
The best-case performance is at -25 ºC, which is -125.1 dBc/Hz, whereas the worst case is at -117.87 dBc/Hz. At the standard temperature of 27 ºC, the phase noise is 122 dBc/Hz. The simulated differential output signal of the TVCO shown in Fig. 14 Figure 15 plots the simulated and measured output voltage waveforms at the drain of M 1 and M 2 . It can be observed that the simulated and measured startup time of the TVCO is 1.5 ns and 2.5 ns, with the corresponding output voltage swing of 1.8 V and 1.7 V, respectively. Figure 16 illustrates the measured FoM and PN across V TUNE . At V TUNE of 700 mV, which corresponds to 2.59 GHz, the FoM and PN achieved are 190.36 dBc/Hz and -122 dBc/Hz, respectively. Table I compares the performance parameters of the proposed TVCO with those obtained in previous reports. The proposed TVCO achieves the highest FoM at a low supply voltage of 0.7 V, which is essential for lowpower 5 th Generation New Radio Application (5G NR).

V. CONCLUSIONS
This paper introduces a tailless 2.5 GHz to 2.67 GHz Class-C LC VCO (TVCO) topology. Theoretical and systematic analysis that determines operation and true oscillation frequency that includes intrinsic parasitic capacitance components is shown. The simulation and measured results showed that a reduced trade-off between phase noise and power consumption was achieved with the proposed TVCO. With the exclusion of the conventional tail current source and dual gate biasing mechanism, this architecture performs better than the traditional Class-C VCO obtaining the phase noise at -122 dBc/Hz at 1 MHz offset under a low supply voltage and power consumption of 0.7 V and 0.98 mW, respectively. The measurements obtained with the TVCO showed a superior FoM performance at 190.36 dBc/Hz compared to other LC VCOs from previous reports. Hence, the TVCO suits the 5G NR technology applications comfortably.

CONFLICTS OF INTEREST
The authors declare that they have no conflicts of interest.