A High Efficiency 1 . 8 W Power Amplifier for Wireless Communications

A power amplifier, implemented in 2µm InGaP/GaAs Heterojunction Bipolar Transistor (HBT) is presented. The size of the fabricated chip is 700 µm × 700 µm. With an integrated input matching network, the PA observes an input return loss (S11) of -22 dB. Biased at low quiescent current of 65 mA, it delivers a maximum output power of 1.8 W with 71 % efficiency at 1.85 GHz. The output return loss (S22) of the PA is -15.2 dB. The output matching network is designed to reduce the mismatch loss between the power amplifier and the antenna without compromising the output power and efficiency. The PA also exhibits a K-factor greater than 1 from DC up to 5 GHz, ensuring unconditional stability. The power gain of the PA is 14.9 dB. The measured results verify that the PA is capable to operate at high efficiency and to deliver high output power with a good output return loss. DOI: http://dx.doi.org/10.5755/j01.eee.20.8.2949


I. INTRODUCTION
Power amplifier (PA) is tasked upon in the amplification of low level signal to a desired output power in a transmitter system.This is accomplished by converting a dc input power to a significant amount of microwave/RF output power [1]- [5].Therefore an efficient transmission is always desired [6]- [10].
Several technologies are utilized in designing PA for various applications in wireless communications.For low voltage application, the HBT technology appears to be prominent.This is due to its inherent characteristic of low collector-emitter offset voltage and low resistance [11]- [13].Moreover, it has superior electrical characteristics at high frequencies [14], which helps to transmit high output power with minimum parasitic loss.The HBT technology inherits low leakage current, thus eliminating the need to have an extra dc switch to turn off the power supply, which is a common practice in GaAs MESFET amplifiers [15].
An efficient power conversion is always desired in realizing a good PA.Often, power losses in HBT PA are due to thermal effect and mismatch loss in the transmitter system.In HBT technology, the former effect is minimized with ballasting technique.In this technique, a resistor is implemented at the base or emitter of a HBT to prevent the collapse of the collector current in the event one of the HBT unit cell operates at a higher temperature [16]- [19].The solution to the latter effect is usually found by designing an antenna respective to the output impedance of the PA.Hence a custom antenna design is always needed.This imposes a great inconvenience to the transmitter system designers.
This paper presents the design of a PA which observes less than -12 dB input and output return loss with maximum output power of 1.8 W. The PA has highest PAE of 71 % and power gain of 14.9 dB, while maintaining a broadband stability factor from DC to 5 GHz.

II. POWER AMPLIFIER DESIGN METHODOLOGY
Figure 1 depicts the schematic of the designed PA, encapsulating the HBT transistor, input matching network, output matching network and bias circuit.
The PA employs common emitter structure in order to achieve reasonable trade-off between gain, output power and efficiency [20].An accurate input impedance matching network is an important criterion since it allows maximum power transfer under a prescribed load condition [21].Hence, the input matching network integrating C2, L1, C4, L3 and C6 has been designed based on the following equation [22] , , 1 PIN, PAVS and MS denotes input power to the amplifier, available power from the signal source and mismatch loss between signal source and input of the PA, respectively.If MS = 1, then all the available power from source will be transferred to the input of the PA.This is quantified by a very low input return loss (S11) in the measurement.The objective of MS = 1 is achieved when the condition is satisfied to be * .
The relationship between ΓIN and S11 is given by 12 21 11 22 1 where S12, S21, S22 and ΓL represents the isolation between  The maximum output power delivered by the PA is determined by its load resistance Rload, defined as max , where Vdc is the desired operating voltage, Vk is the I-V curve knee voltage and Imax is the maximum current obtained if the device is biased at class-A biasing point.In order to achieve a high PAE with low quiescent collector current, a deep class-AB biasing point is executed, as illustrated in Rload represents the load resistance of a single unit cell HBT.Since in HBT, the amplifier is built with multiple unit cells, the load resistance is scaled accordingly to the number of unit cell required to deliver the desired maximum output power.Hence the optimum load resistance, Rload-opt is given by [14] , where Rload-opt defines the HBT device size.The appropriate device dimension ensures minimum tradeoff between maximum output power, PAE and output return loss.In Fig. 1 the proposed output matching network transforms 50 Ω load impedance to Rload-opt.Referring to Fig. 1, L2 is the bondwires which connects the die to the PCB.L4 is a SMT coil which is capable of holding current up to the level of 2 A. L2, C1 and C3 ensure a maximum output power and PAE is delivered by the PA.The PAE is defined as 100%.
Pout represents the output power, whereas Pin and Pdc reflects the input power and DC power, respectively.The maximum output power transferred can be expressed as [23]  .10 Referring to Fig. 1, L4 and C5 help to deliver PA's output return loss to be less than -10 dB.
Another important parameter which has been given due priority in this work is the unconditionally stability factor, which known as the Rollett factor, K [24].The power amplifier has been designed to meet this criterion, which is conditioned as [25] In the effort to design the biasing circuit for the PA, current mirror technique is adapted.In Fig. 1, Q1 acts as a single current mirror to bias up the amplifier.Transistor Q2 has been added in a cascode integration with Q1 in order to present a high output resistance, which stabilizes the bias circuit over supply voltage variation.Resistor R1 acts as a feedback resistor to stabilize Q2.Transistor Q3 and Q4 are a diode connected HBT, which is integrated at the base of Q1 to exhibit enhanced temperature compensation.Capacitor C7 helps to mitigate the bias modulation effect.Bias modulation effect is a phenomenon where the bias circuit is modulated by the input modulating signal due to the presence of low impedance at bias circuit output, which is the output of Q2 referring to the architecture in Fig. 1 [26], [27].

III. MEASUREMENT RESULTS
Figure 3 illustrates the fabricated 700 µm × 700 µm PA using the platform of 2 µm InGaP/GaAs Heterojunction Bipolar Transistor (HBT) technology.This enables the PA to be connected to the baseband-chip in the wireless transmitter line-up with a very minimum input mismatch loss.On the other hand, the S22 is -15.2 dB, which helps to reduce the mismatch loss between a 50 Ω antenna and output of PA.The power gain of the PA is 14.9 dB at 1.85 GHz.
Figure 5 depicts the stability plot.It can be observed that the PA has a K-factor more than 1 from DC up to 5 GHz.The good out of band stability of the PA serves to be an added advantage, as the requirement to integrate a filter at the output of the PA is alleviated.The K-Factor greater than 1 indicates PA is unconditionally stable.Figure 6 illustrates the gain and PAE plot respective to the output power at operating frequency of 1.85 GHz.The maximum output power delivered by the PA is 32.5 dBm, which is equal to 1.8 W. The gain variation is observed to be less than 1 dB up to PA's 1 dB compression point which indicates a linear transmission.The 1 dB compression point is 31.5 dBm.The highest efficiency is 71 %, thus approximates close to an ideal Class-B PA's efficiency.The performance of the fabricated PA is summarized in Table I.IV.CONCLUSIONS In this work, the design of a 1.8 W PA for 1.85 GHz operating frequency is demonstrated.Materialized in an InGaP/GaAs HBT technology with an active chip area of 700 µm × 700 µm, the PA delivers a maximum PAE of 71 %, thus enhancing the battery life.On the other hand, the PA exhibits a respective S11 of -22.3 dB and S22 of -15.2 dB.These results prove that the proposed PA serves to be a prominent solution in reducing the mismatch loss between PA and antenna in a wireless transmitter system while delivering a significant amount of output power and PAE.

Fig. 2 .
Fig. 2. A deep class-AB bias point reflects a bias point closer to Class-B operation.For VCE = 5 V and Ibb = 9 mA, Vbe = 1.31V.Rload represents the load resistance of a single unit cell HBT.Since in HBT, the amplifier is built with multiple unit cells, the load resistance is scaled accordingly to the number of unit cell required to deliver the desired maximum output power.Hence the optimum load resistance, Rload-opt is given by[14]

Figure 4
Figure4depicts the small signal performance of the PA.The PA exhibits good S11 which is -22.3 dB at 1.85 GHz.This enables the PA to be connected to the baseband-chip in the wireless transmitter line-up with a very minimum input mismatch loss.On the other hand, the S22 is -15.2 dB, which helps to reduce the mismatch loss between a 50 Ω antenna and output of PA.The power gain of the PA is 14.9 dB at 1.85 GHz.

Fig. 5 .
Fig. 5. K-Factor > 1 up to 5 GHz (From DC to 1.4 GHz and from 3.5 GHz to 5 GHz, K-Factor is more than 3).

TABLE I .
PA PERFORMANCE SUMMARY.